The present trend toward increased integration has led to designing integrated circuits which include, on a single semiconductor material chip, a large variety of electronic components having structural and functional features which may be widely different from one another. Thus, monolithic structures have been provided, including CMOS (Complementary Metal Oxide Semiconductor) circuits for processing digital signals, bipolar circuits for amplifying analog signals, power components of both the DMOS (Diffused Metal Oxide Semiconductor) and the bipolar types for generating and controlling high voltages and large currents.
Such structures are formed in large numbers on the same semiconductor material slice by means of several successive chemiophysical treatments which include, in a known manner, high-temperature treatments, deposition of insulative and conductive layers, chemical etching, and implantation of dopants.
In view of the fact that each of the above steps contributes to manufacturing faults in varying degrees, and increases the risk of breaking the slice, an important designer's task is to provide the largest possible number of components using minimum variations in the manufacturing process.
In certain cases, a complex integrated circuit may require that buried Zener diodes, high-speed bipolar transistors, field-effect junction transistors, and other components be formed which need a buried region wherein the concentration and/or depth of the impurities can be determined with great accuracy and as independently as possible of variations in the processing parameters. In these cases, specific masking and doping steps are employed, in addition to those already required for the formation of the other integrated circuit components. To avoid these steps, some compromises are occasionally accepted. For instance, in a process for manufacturing an integrated circuit which includes field-effect complementary transistors of the MOS forming the N-type source and drain regions of the N-channel MOS transistors in the CMOS pairs, and a plurality of steps for forming the P-type source and drain regions of the P-channel MOS transistors in the CMOS pairs. In particular, this involves forming a mask to define the source and drain areas of the two transistors, implanting impurities of a first type such as arsenic, implanting impurities of a second type such as boron, and a thermal treatment, possibly in several successive steps to meet specific process requirements, in order to allow the implanted impurities to diffuse and to obtain N and P regions having specified depths and concentrations.
To add Zener-type diodes, i.e., diodes with a predetermined reverse breakdown voltage, to an integrated circuit, a proposal has been made to use in overlapping relationship, the same N and P implants described above, in the same order to form the source and drain regions of the CMOS transistors, based on the fact that boron has a greater coefficient of diffusion through silicon than arsenic. In actual practice, the following operations are performed: the mask that defines the source and drain areas of the N-channel transistors is also apertured to define the areas for the cathode regions of the diodes; arsenic atoms are implanted in the silicon through these apertures in the same way the atoms are implanted through the source and drain apertures; a heating step is carried out at a high temperature to initially diffuse the arsenic atoms; the mask which defines the source and drain areas for the P-channel transistors is also apertured to define areas for doping the anode regions of the diodes within the cathode areas; through these apertures, boron atoms are implanted in the silicon in the same way they are implanted through the source and drain apertures for the P-channel transistors; and finally, a heating step is carried out at a high temperature to further diffuse the arsenic atoms diffuse the boron atoms through the arsenic and underlying silicon until a buried region of the P type, which constitutes the active anode region of the diode is obtained, which forms a junction with the N region which constitutes the cathode region of the diode.
It has been found that the Zener diodes thus obtained have a reverse breakdown voltage which varies within very broad limits, e.g., in the 5 V to 8 V range, due to such uncontrollable process parameters as the thickness of the thin isolation oxide which is usually grown on the silicon surface prior to the boron implantation, the concentration of arsenic atoms in the N region, and the boron implantation energy. In order to reduce this excessive dependence of the breakdown voltage on the process parameters, a proposal has been made to increase the depth of the boron penetration into the N region by increasing the implantation dosage and/or energy. This yields, however, diodes which have a fairly gradual reverse breakdown characteristic due to a marked reverse current contribution from a tunneling effect at a low reverse voltage (2-4 V). Moreover, the source and drain regions of the P-channel transistors, which are formed by the same implantation, generally need to be modified, thereby introducing a deviation from the ideal design parameters of the CMOS pair. Similar problems to the above are encountered where high-speed bipolar transistors or junction field-effect transistors (JFET) are to be formed in the same integrated circuit without adding new process steps.